diff --git a/CHANGELOG.md b/CHANGELOG.md
index 36806f3b2d..9529ff6e52 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -8,6 +8,7 @@ Please mark all change in change log and use the issue from GitHub
 -   \#2585 IVF_PQ on GPU with using metric_type IP
 -   \#2578 Result count doesn't match target vectors count
 -   \#2557 fix random crash of INSERT_DUPLICATE_ID case
+-   \#2598 fix Milvus docker image report illegal instruction
 
 ## Feature
 
diff --git a/core/src/index/thirdparty/faiss/utils/instruction_set.h b/core/src/index/thirdparty/faiss/utils/instruction_set.h
index a20141f714..90ccc2c368 100644
--- a/core/src/index/thirdparty/faiss/utils/instruction_set.h
+++ b/core/src/index/thirdparty/faiss/utils/instruction_set.h
@@ -3,6 +3,7 @@
 
 #include <array>
 #include <bitset>
+#include <cpuid.h>
 #include <cstring>
 #include <iostream>
 #include <string>
@@ -10,58 +11,6 @@
 
 namespace faiss {
 
-#if defined(__i386__) && defined(__PIC__)
-
-/* %ebx may be the PIC register.  */
-#if __GNUC__ >= 3
-
-#define __cpuid(level, a, b, c, d)           \
-    __asm__(                                 \
-        "xchg{l}\t{%%}ebx, %1\n\t"           \
-        "cpuid\n\t"                          \
-        "xchg{l}\t{%%}ebx, %1\n\t"           \
-        : "=a"(a), "=r"(b), "=c"(c), "=d"(d) \
-        : "0"(level))
-
-#define __cpuid_count(level, count, a, b, c, d) \
-    __asm__(                                    \
-        "xchg{l}\t{%%}ebx, %1\n\t"              \
-        "cpuid\n\t"                             \
-        "xchg{l}\t{%%}ebx, %1\n\t"              \
-        : "=a"(a), "=r"(b), "=c"(c), "=d"(d)    \
-        : "0"(level), "2"(count))
-
-#else /* __GNUC__ >= 3 */
-
-/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
-   nor alternatives in i386 code.  */
-#define __cpuid(level, a, b, c, d)           \
-    __asm__(                                 \
-        "xchgl\t%%ebx, %1\n\t"               \
-        "cpuid\n\t"                          \
-        "xchgl\t%%ebx, %1\n\t"               \
-        : "=a"(a), "=r"(b), "=c"(c), "=d"(d) \
-        : "0"(level))
-
-#define __cpuid_count(level, count, a, b, c, d) \
-    __asm__(                                    \
-        "xchgl\t%%ebx, %1\n\t"                  \
-        "cpuid\n\t"                             \
-        "xchgl\t%%ebx, %1\n\t"                  \
-        : "=a"(a), "=r"(b), "=c"(c), "=d"(d)    \
-        : "0"(level), "2"(count))
-
-#endif /* __GNUC__ >= 3 */
-
-#else /* defined(__i386__) && defined(__PIC__) */
-
-#define __cpuid(level, a, b, c, d) __asm__("cpuid\n\t" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(level))
-
-#define __cpuid_count(level, count, a, b, c, d) \
-    __asm__("cpuid\n\t" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(level), "2"(count))
-
-#endif /* defined(__i386__) && defined(__PIC__) */
-
 class InstructionSet {
  public:
     static InstructionSet&